1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having terminal members which function as relay members for connecting a semiconductor element and leads to each other.
2. Description of the Prior Art
Recently, there have been requirements to provide semiconductor integrated circuit devices having an increased integration density and an increased number of external pins. In order to meet the above requirement, a semiconductor device has been proposed in which a small-sized semiconductor element is mounted on a semiconductor device having a large number of pins. In such a semiconductor device, it is required that the ends of inner leads be positioned close to pads of the semiconductor element so that wire bonding can be carried out. As the number of terminals increases, the distance between adjacent inner leads decreases. In the currently available lead frame production technology, it becomes very difficult to position the ends of the inner leads so that they are close to the semiconductor element in a state where the inner leads have enough mechanical strength to withstand against the wire bonding.
In order to fabricate the above-mentioned semiconductor device with the current wire bonding technology, there has been proposed use of terminal members (relay members on which electrically conductive patterns are formed in order to connect pats formed on the semiconductor element and the inner leads (see Japanese Laid-Open Patent Publication No. 60-234335). The ends of the inner leads and opposing ends of the conductive patterns are connected to each by wire bonding, and pads of the semiconductor element and other ends of the conductive patterns are connected to each other by wire bonding. The terminal members are formed on a lead frame stage. During a step of forming the lead frame stage, the terminal members are integrally formed with the lead frame stage so that the terminal members are located outside a mounting position of the semiconductor element on the lead frame stage. Then, the electrically conductive patterns are formed on upper surfaces of the electrically conductive patterns by an etching or the like.
However, the semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 60-234335 has the following disadvantages. It is troublesome to form the lead frame stage because the terminal members are integrally formed with the lead frame stage. Further, a complex process is needed to form the conductive patterns on the terminal members integrated with the lead frame stage. As a result, it is very difficult to efficiently produce the semiconductor devices.
Japanese Laid-Open Patent Publication No. 60-234335 does not show what material is suitable for the terminal members. However, it is very important to select a proper material for making the terminal members. If the terminal members are made of a soft material, such as glass epoxy, a failure in bonding will take place. Normally, an ultrasonic bonding process is used for wire bonding. During the bonding process, such soft terminal members are vibrated while they are maintained at a high temperature.